Technology

Nano ePrint has developed and patented a unique architecture for constructing electronic devices and circuits. Our planar nano-transistors (PNTs) are dramatically simpler than traditional field effect transistors (FETs), and deliver higher performance in a wide range of semiconductor materials. Planar nano-diodes (PNDs) can also be constructed via a similar approach.

Using this architecture, Nano ePrint can fabricate electronic devices in a single layer of thin-film semiconductor, deposited on a flexible substrate, using a single-step patterning approach. The patterning is performed using nano-embossing, analogous to the earliest forms of printing (wood block, letterpress, etc) but on a much finer scale. This printing process is compatible with roll-to-roll, and has been in use commercially for around 20 years for the production of optical microstructures (such as the security holograms that are embedded in modern bank notes and passports).

Because PNTs and PNDs are fabricated within the semiconductor layer itself, they do not require dielectric materials, or conductive contacts for source, drain and gate. Eliminating this conventional multi-layer material stack also eliminates the registration issues of aligning successive material or process steps while dealing with a flexible substrate. This allows much smaller feature sizes, resulting in both dramatically reduced circuit footprint and significantly increased performance.

Interconnect is also improved using Nano ePrint’s approach. For relatively simple circuits or functional units – such as logic gates (AND, OR, NOT, etc) and basic analogue blocks (rectifier, amplifier, modulator, etc) – the interconnect between adjacent PNTs and PNDs can be achieved directly within the semiconductor layer. For more complex circuits, a separate conductive interconnect layer may still be required, but the routing problem is substantially simplified.